1. Field of the Invention
This invention relates to a semiconductor integrated circuit device, and more particularly to the technique for applying a back gate bias to a four-terminal transistor in an LSI.
2. Description of the Related Art
With the recent miniaturization of LSI devices, the power supply voltage has been getting lower and therefore currents flowing in the well regions and the semiconductor substrate have been becoming smaller. As a result, the resistances of the well regions are almost negligible, which makes smaller the problems of the occurrence of latch-up and fluctuations in the voltages at the well regions and the semiconductor substrate. Normally, each circuit is composed of three-terminal transistors. In a three-terminal transistor, since the source and the back gate have the same potential (if the transistor is a p-channel MOS transistor, they are at a power supply voltage VDD, and if the transistor is an n-channel MOS transistor, they are at the ground potential GND), the back gate (well region) is connected to the power supply via metal wiring or the like.
However, the circuit section which has to adjust the threshold voltage of the MOS transistor requires a four-terminal transistor capable of setting the back gate to a potential different from that of the source. Such a circuit section is formed in a well region electrically separated from the semiconductor substrate and other well regions. Then, a well bias potential is applied to the circuit section. For example, in the case of n-channel MOS transistors, a p-well region in which an n-channel MOS transistor is to be formed is enclosed by an n-well region. Under these p-well region and n-well region, a deep n-well region is formed, thereby separating the p-well region electrically from the semiconductor substrate and other well regions. Then, a well bias potential is applied via metal wiring or the like to the p-well region, thereby applying a back gate bias (refer to, for example, Jpn. Pat. Appln. KOKAI Publication No. H11-251447).
As described above, since the semiconductor integrated circuit device using four-terminal transistors requires new wiring for applying a potential to the back gate to be added, which causes the problem of making the die size larger than when using three-terminal transistors.